Semiconductor package and fabrication method thereof

ABSTRACT

A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor packages and fabricationmethods thereof, and more particularly, to a high-reliabilitysemiconductor package and a fabrication method thereof.

2. Description of Related Art

Along with the rapid development of electronic industries, electronicproducts are developed towards multi-function and high performance. Tomeet the miniaturization requirement of semiconductor packages, waferlevel packaging (WLP) technologies have been developed.

U.S. Pat. No. 6,452,265 and U.S. Pat. No. 7,202,107 provide fabricationmethods of wafer-level packages. FIGS. 1A to 1E are schematiccross-sectional views showing a fabrication method of a conventionalsemiconductor package 1.

Referring to FIG. 1A, a thermal release adhesive layer 11 is applied ona carrier 10. The thermal release tape 11 loses its adhesive propertywhen heated.

Referring to FIG. 1B, a plurality of chips 12 are disposed on thethermal release adhesive layer 11. Each of the chips 12 has an activesurface 12 a with a plurality of electrode pads 120 and an inactivesurface 12 b opposite to the active surface 12 a, and is disposed on thethermal release adhesive layer 11 via the active surface 12 a thereof.

Referring to FIG. 1C, an encapsulant 13 is formed on the chips 12 andthe thermal release tape 11 through molding.

Referring to FIG. 1D, the thermal release adhesive layer 11 and thecarrier 10 are removed by heating, thereby exposing the active surfaces12 a of the chips 12.

Referring to FIG. 1E, a circuit structure 14 is formed on theencapsulant 13 and the active surfaces 12 a of the chips 12 andelectrically connected to the electrode pads 120 of the chips 12.

However, since the thermal release adhesive layer 11 is adhesive and thedifference of CTEs (Coefficient of Thermal Expansion) between thethermal release adhesive layer 11 and the carrier 10 is substantial,after the encapsulant 13 is formed, warpage can easily occur to theoverall structure during a thermal cycle, thus reducing the productreliability.

Further, it is difficult to uniformly coat the thermal release adhesivelayer 11 on a large-sized carrier 10. Therefore, the thermal releaseadhesive layer is preferably coated on a small-sized carrier 10.However, in comparison to a large-sized carrier, it is more difficultfor the conveying equipment (not shown) to transport such a small-sizedcarrier, thereby adversely affecting the production efficiency.

Therefore, how to overcome the above-described drawbacks has becomecritical.

SUMMARY OF THE INVENTION

In view of the above-described drawbacks, the present invention providesa semiconductor package, which comprises: an encapsulant having a firstsurface formed with a protruding portion and a second surface oppositeto the first surface; a chip embedded in the protruding portion of theencapsulant, wherein the chip has an active surface with a plurality ofelectrode pads and an inactive surface opposite to the active surface,the active surface and the electrode pads being exposed from theprotruding portion of the encapsulant; a circuit structure formed on thefirst surface of the encapsulant and the active surface of the chip andelectrically connected to the electrode pads of the chip; and a bondinglayer formed on the second surface of the encapsulant.

The present invention further provides a fabrication method of asemiconductor package, which comprises the steps of: providing a carrierhaving a plurality of concave portions on a surface thereof and arelease layer formed on the surface having the concave portions;disposing a plurality of chips on the release layer in the concaveportions, respectively, wherein each of the chips has an active surfacewith a plurality of electrode pads and an inactive surface opposite tothe active surface, the chip being disposed on the release layer via theactive surface thereof; forming an encapsulant on the chips and therelease layer; forming a bonding layer on the encapsulant; removing therelease layer and the carrier so as to expose the active surfaces of thechips; and forming a circuit structure on the encapsulant and the activesurfaces of the chips so as to electrically connect the circuitstructure and the electrode pads of the chips.

In the above-described method, the carrier can be made of glass ormetal, and the release layer can be made of a hydrophobic material, aninorganic material or a high polymer.

In the above-described method, the release layer can be formed throughplasma-enhanced chemical vapor deposition (PECVD), and the bonding layercan be formed through lamination.

The above-described method can further comprise performing a singulationprocess so as to obtain a plurality of semiconductor packages.

Before removing the release layer and the carrier, the method canfurther comprise forming an isolation layer on the bonding layer,wherein the isolation layer is formed on a support plate so as to besandwiched between the support plate and the bonding layer. Further,before forming the bonding layer on the encapsulant, the method canfirst sandwich the isolation layer between the support plate and thebonding layer. Therein, the isolation layer is not adhesive to thesupport plate and the bonding layer.

The isolation layer can be patterned to form gaps therein and then theisolation layer can be embedded in the bonding layer such that a portionof the bonding layer is formed in the gaps for bonding with the supportplate. After forming the circuit structure, the method can furthercomprise cutting the overall structure along cutting paths through thegaps so as to remove the isolation layer and the support plate, therebyobtaining a plurality of semiconductor packages. Alternatively, the areaof the isolation layer can be less than the area of the bonding layerand the area of the support plate such that a portion of the bondinglayer encapsulates the edges of the isolation layer for the bondinglayer to be bonded with the edges of the support plate. As such, afterforming the circuit structure, the method can further comprisesingulating the chips and cutting along the edges of the isolation layerso as to remove the support plate and the isolation layer, therebyobtaining a plurality of semiconductor packages.

In the above-described semiconductor package and method, the bondinglayer can be made of polyimide (PI), a dry film or a semi-dry material.

In the above-described semiconductor package and method, the circuitstructure can have at least a dielectric layer formed on the encapsulantand the active surface of the chip, a circuit layer formed on thedielectric layer and a plurality of conductive vias formed in thedielectric layer for electrically connecting the circuit layer and theelectrode pads of the chip.

Further, an insulating protection layer can be formed on the outermostdielectric layer of the circuit structure and have a plurality ofopenings therein such that a portion of the circuit layer is exposedthrough the openings so as for conductive elements to be disposedthereon through the openings.

In other embodiments, the circuit structure can have at least adielectric layer formed on the encapsulant, and a circuit layer formedon the dielectric layer and the active surface of the chip so as toelectrically connect the electrode pads of the chip.

Therefore, by providing the release layer that is only slightly adhesiveto the chips and the encapsulant, the present invention avoids warpageof the overall structure during a thermal cycle caused by incompatibleCTEs. Further, the release layer can be easily formed on a carrier oflarge size through PECVD, thereby facilitating transport and improvingthe production efficiency.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1E are schematic cross-sectional views showing a fabricationmethod of a conventional semiconductor package; and

FIGS. 2A to 2H are schematic cross-sectional views showing a fabricationmethod of a semiconductor package according to the present invention,wherein FIG. 2E′ shows another embodiment of FIG. 2E, and FIGS. 2G′, 2G″and 2H′ show other embodiments of FIGS. 2G and 2H, respectively.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following illustrative embodiments are provided to illustrate thedisclosure of the present invention, these and other advantages andeffects can be apparent to those in the art after reading thisspecification.

It should be noted that the drawings are only for illustrative purposesand not intended to limit the present invention. Meanwhile, terms suchas ‘on’, ‘a’ etc. are only used as a matter of descriptive convenienceand not intended to have any other significance or provide limitationsfor the present invention.

FIGS. 2A to 2H are schematic cross-sectional views showing a fabricationmethod of a semiconductor package 2 according to the present invention.

Referring to FIG. 2A, a carrier 20 having a plurality of concaveportions 200 on a surface thereof is provided. In the presentembodiment, the carrier 20 is made of glass or metal, and the concaveportions 200 are array arranged on the carrier 20.

Referring to FIG. 2B, a release layer 21 is formed on the surface of thecarrier 20 having the concave portions 200.

In the present embodiment, the release layer 21 is made of a hydrophobicmaterial, an inorganic material or a high polymer such aspoly-para-xylylene (parylene), and formed through plasma-enhancedchemical vapor deposition (PECVD).

Further, the release layer 21 can be easily formed on the carrier 20 oflarge size through PECVD, thereby facilitating transport of the carrier20 and improving the production efficiency.

Referring to FIG. 2C, a plurality of chips 22 are disposed on therelease layer 21 in the concave portions 200, respectively. Each of thechips 22 has an active surface 22 a with a plurality of electrode pads220 and an inactive surface 22 b opposite to the active surface 22 a,and the chip 22 is disposed on the release layer 21 via the activesurface 22 a thereof.

The concave portions 200 facilitate alignment of the chips 22 so as toavoid position deviation. Further, since the release layer 21 is onlyslightly adhesive to the chips 22 in comparison to the conventionalthermal release adhesive layer, the present invention avoids significantposition deviations of the chips 22 caused by the CTE of the releaselayer 21, thereby securing the chips 22 in position and improving thereliability of subsequent processes.

Referring to FIG. 2D, an encapsulant 23 is formed on the chips 22 andthe release layer 21 by laminating or coating so as to encapsulate thechips 22.

In the present embodiment, the encapsulant 23 can be made of, but notlimited to, polyimide (PI). The release layer 21 is slightly adhesive tothe encapsulant 23.

Referring to FIGS. 2D and 2E, a bonding layer 27 is laminated on theencapsulant 23 through a support plate 29, and an isolation layer 28 islaminated in the bonding layer 27.

In the present embodiment, the bonding layer 27 has a thickness of 10 to100 um. The bonding layer 27 can be made of polyimide (PI), a dry filmor a semi-dry material. The support plate 29 can be made of glass.

Further, the isolation layer 28 is neither adhesive to the bonding layer27 (such as PI) nor adhesive to the support plate 29 (such as glass),and the bonding layer 27 (such as PI) is adhesive to the support plate29 (such as glass). Therefore, in the fabrication process, the isolationlayer 28 is first patterned to form gaps 280 therein and then laminatedsuch that the bonding layer 27 is pressed into the gaps 280 for bondingwith the support plate 29.

Referring to FIG. 2D, in the present embodiment, the bonding layer 27,the isolation layer 28 and the support plate 29 are laminatedsimultaneously. In other embodiment, the bonding layer 27 can be formedon the encapsulant 23 first and then the isolation layer 28 is pressedinto the bonding layer 27 through the support plate 29.

In another embodiment, referring to FIG. 2E′, the isolation layer 28′can have an area less than the area of the bonding layer 27 and the areaof the support plate 29. As such, during the lamination process, aportion of the bonding layer 27 is pressed to encapsulate the edges ofthe isolation layer 28′ so as to bond the bonding layer 27 with theedges of the support plate 29.

Referring to FIG. 2F, the release layer 21 and the carrier 20 areremoved to expose the active surfaces 22 a of the chips 22 and aplurality of protruding portions 230 of the encapsulant 23.

In the present embodiment, the carrier 20 is first removed from therelease layer 21 and then the release layer 21 is removed throughplasma. Since the release layer 21 is removed without the need to applyheat, the present invention avoids warpage of the overall structureduring a thermal cycle.

Furthermore, the support plate 29 is provided to serve as a carrierduring the removal process since the overall structure needs to be movedto another machine and turned upside down for the removal process.

Referring to FIG. 2G a circuit structure 24 is formed on the encapsulant23 and the active surfaces 22 a of the chips 22 and electricallyconnected to the electrode pads 220 of the chips 22.

In the present embodiment, the circuit structure 24 has at least adielectric layer 240 formed on the encapsulant 23 and the activesurfaces 22 a of the chips 22, a circuit layer 241 formed on thedielectric layer 240 and a plurality of conductive vias 242 formed inthe dielectric layer 230 for electrically connecting the circuit layer241 and the electrode pads 220 of the chips 22. Subsequently, aninsulating protection layer 25 is formed on the outermost dielectriclayer 240 and a plurality of openings 250 are formed in the insulatingprotection layer 25 such that a portion of the circuit layer 241 isexposed through the openings 250 so as for conductive elements 26 to bedisposed thereon.

Therein, the number of the dielectric layers 240 can be multiple so asto increase the number of the circuit layers 241. The insulatingprotection layer 25 has a thickness of 30 to 500 um. The insulatingprotection layer 25 can be made of SiO₂ or silicon nitride so as toserve as a passivation layer. The insulating protection layer 25 canalso be made of a reinforcing material such as polyimide (PI) andpolybenzoxazole (PBO).

The conductive elements 26 can be, but not limited to, solder balls,solder bumps or solder pins.

In another embodiment, referring to FIG. 2G′, the circuit structure 24can have at least a dielectric layer 240 formed on the encapsulant 23,and a circuit layer 241 formed on the dielectric layer 240 and theactive surfaces 22 a of the chips 22 for electrically connecting theelectrode pads 220 of the chips 22.

The present invention forms the encapsulant 23 to encapsulate the chips22 through laminating or coating instead of molding and then forms thecircuit structure 24 of large size through patterning, thus effectivelyreducing the fabrication cost.

Referring to FIGS. 2H and 2H′, a laser cutting tool or saw blade is usedto perform a singulation process along cutting lines L (as shown in FIG.2G) through the gaps 280 so as to obtain a plurality of semiconductorpackages 2, 2′.

In the present embodiment, by cutting through the gaps 280 in theisolation layer 28, the bonding between the bonding layer 27 and thesupport plate 29 is eliminated. As such, the support plate 29 togetherwith the isolation layer 28 can be removed. Therefore, the sandwichstructure consisting of the support plate 29, the isolation layer 28 andthe bonding layer 27 facilitates to obtain the semiconductor packages 2after the cutting process.

In another embodiment, continued from FIG. 2E′, a singulation process isperformed along cutting lines L′ (as shown in FIG. 2G″) around the chips22 and further along cutting lines L″ (as shown in FIG. 2G″) at theedges of the isolation layer 28′ so as to remove the support plate 29and the isolation layer 28.

The present invention further provides a semiconductor package 2, 2′,which has: an encapsulant 23 having a first surface 23 a and a secondsurface 23 b opposite to the first surface 23 a; a chip 22 embedded inthe encapsulant 23; a circuit structure 24 formed on the encapsulant 23;and a bonding layer 27 formed on the second surface 23 b of theencapsulant 23.

The first surface 23 a of the encapsulant 23 has a protruding portion230.

The chip 22 is embedded in the protruding portion 230 and has an activesurface 22 a with a plurality of electrode pads 220 and an inactivesurface 22 b opposite to the active surface 22 a, and the active surface22 a and the electrode pads 220 are exposed from the protruding portion230 of the encapsulant 23.

The bonding layer 27 is made of PI, a dry film or a semi-dry film.

The circuit structure 24 is formed on the first surface 23 a of theencapsulant 23 and the active surface 22 a of the chip 22 andelectrically connected to the electrode pads 220 of the chip 22. Thecircuit structure 24 has at least a dielectric layer 240 formed on theencapsulant 23 and the active surface 22 a, a circuit layer 241 formedon the dielectric layer 240 and a plurality of conductive vias 242formed in the dielectric layer 240 for electrically connecting thecircuit layer 241 and the electrode pads 220 of the chip 22.

Alternatively, the circuit structure 24 has at least a dielectric layer240 formed on the encapsulant 23 and a circuit layer 241 formed on thedielectric layer 240 and the active surface 22 a of the chip 22 forelectrically connecting the electrode pads 220 of the chip 22.

Furthermore, an insulating protection layer 25 is formed on theoutermost dielectric layer 240 of the circuit structure 24 and has aplurality of openings 250 therein such that portions of the circuitlayer 241 are exposed through the openings 250 so as for conductiveelements 26 to be disposed thereon. Moreover, in other embodiments, thecircuit structure 24 can have multiple circuit layers.

Therefore, by providing the release layer that is only slightly adhesiveto the chips and the encapsulant, the present invention avoids warpageof the overall structure, thereby effectively improving the productreliability.

Further, the release layer can be easily formed on a carrier of largesize so as to facilitate transport and improve the productionefficiency.

Furthermore, by forming the encapsulant through laminating or coatingand then forming the circuit structure of large size through patterning,the present invention reduces the fabrication cost.

Moreover, since the isolation layer is neither adhesive to the bondinglayer nor adhesive to the support plate, by cutting through the gaps inthe isolation layer to eliminate the bonding between the bonding layerand the support plate, the present invention can conveniently remove thesupport plate and the isolation layer so as to obtain a plurality ofsemiconductor packages.

The above-described descriptions of the detailed embodiments are only toillustrate the preferred implementation according to the presentinvention, and it is not to limit the scope of the present invention.Accordingly, all modifications and variations completed by those withordinary skill in the art should fall within the scope of presentinvention defined by the appended claims.

What is claimed is:
 1. A semiconductor package, comprising: anencapsulant having a first surface formed with a protruding portion anda second surface opposite to the first surface; a chip embedded in theprotruding portion of the encapsulant, wherein the chip has an activesurface with a plurality of electrode pads and an inactive surfaceopposite to the active surface, the active surface and the electrodepads being exposed from the protruding portion of the encapsulant; acircuit structure formed on the first surface of the encapsulant and theactive surface of the chip and electrically connected to the electrodepads of the chip; and a bonding layer formed on the second surface ofthe encapsulant.
 2. The package of claim 1, wherein the circuitstructure has at least a dielectric layer formed on the encapsulant andthe active surface of the chip, a circuit layer formed on the dielectriclayer, and a plurality of conductive vias formed in the dielectric layerfor electrically connecting the circuit layer and the electrode pads ofthe chip.
 3. The package of claim 2, further comprising an insulatingprotection layer formed on the outermost one of the at least adielectric layer of the circuit structure and having a plurality ofopenings formed therein such that a portion of the circuit layer isexposed through the openings so as for conductive elements to bedisposed thereon.
 4. The package of claim 1, wherein the circuitstructure has at least a dielectric layer formed on the encapsulant, anda circuit layer formed on the dielectric layer and the active surface ofthe chip so as to electrically connect the electrode pads of the chip.5. The package of claim 1, wherein the bonding layer is made ofpolyimide (PI), a dry film or a semi-dry material.
 6. A fabricationmethod of a semiconductor package, comprising the steps of: providing acarrier having a plurality of concave portions on a surface thereof anda release layer formed on the surface having the concave portions;disposing a plurality of chips on the release layer in the concaveportions, respectively, wherein each of the chips has an active surfacewith a plurality of electrode pads and an inactive surface opposite tothe active surface, the chips being disposed on the release layer viathe active surfaces thereof; forming an encapsulant on the chips and therelease layer; forming a bonding layer on the encapsulant; removing therelease layer and the carrier so as to expose the active surfaces of thechips; and forming a circuit structure on the encapsulant and the activesurfaces of the chips so as to electrically connect the circuitstructure and the electrode pads of the chips.
 7. The method of claim 6,wherein the carrier is made of glass or metal.
 8. The method of claim 6,wherein the release layer is made of a hydrophobic material, aninorganic material or a high polymer.
 9. The method of claim 6, whereinthe release layer is formed through plasma-enhanced chemical vapordeposition (PECVD).
 10. The method of claim 6, wherein the bonding layeris formed through lamination.
 11. The method of claim 6, wherein thebonding layer is made of polyimide (PI), a dry film or a semi-drymaterial.
 12. The method of claim 6, wherein the circuit structure hasat least a dielectric layer formed on the encapsulant and the activesurfaces of the chips, a circuit layer formed on the dielectric layerand a plurality of conductive vias formed in the dielectric layer forelectrically connecting the circuit layer and the electrode pads of thechips.
 13. The method of claim 12, further comprising forming aninsulating protection layer on the outermost one of the at least adielectric layer of the circuit structure and forming a plurality ofopenings in the insulating protection layer such that a portion of thecircuit layer is exposed through the openings so as for conductiveelements to be disposed thereon.
 14. The method of claim 6, wherein thecircuit structure has at least a dielectric layer formed on theencapsulant and a circuit layer formed on the dielectric layer and theactive surfaces of the chips for electrically connecting the electrodepads of the chips.
 15. The method of claim 6, before removing therelease layer and the carrier, further comprising forming an isolationlayer on the bonding layer, wherein the isolation layer is disposed on asupport plate so as to be sandwiched between the support plate and thebonding layer.
 16. The method of claim 15, before forming the bondinglayer on the encapsulant, further comprising sandwiching the isolationlayer between the support plate and the bonding layer.
 17. The method ofclaim 15, wherein the isolation layer is free from being adhered to thesupport plate and the bonding layer.
 18. The method of claim 15, whereinthe isolation layer is patterned to form gaps therein and then theisolation layer is embedded in the bonding layer such that portions ofthe bonding layer are positioned in the gaps for bonding with thesupport plate.
 19. The method of claim 18, after forming the circuitstructure, further comprising cutting the overall structure alongcutting paths through the gaps so as to remove the isolation layer andthe support plate, thereby obtaining a plurality of semiconductorpackages.
 20. The method of claim 15, wherein the isolation layer isless in area than the bonding layer and the support plate such a portionof the bonding layer encapsulates edges of the isolation layer for thebonding layer to be bonded with edges of the support plate.
 21. Themethod of claim 20, after forming the circuit structure, furthercomprising singulating the chips and cutting along the edges of theisolation layer so as to remove the support plate and the isolationlayer, thereby obtaining a plurality of semiconductor packages.
 22. Themethod of claim 6, further comprising performing a singulation processso as to obtain a plurality of semiconductor packages.